Semiconductor devices, such as microprocessors, dynamic random access memory (DRAM), and flash memory, are fabricated in a known manner on a semiconductor wafer. Depending upon the size of the wafer and of each device formed thereon, there may be as many as several hundred devices on a single wafer. These devices are typically identical to one another, each including a plurality of conductive terminals on the surface thereof for power and other connections to the devices such as input signals, output signals, control signals and the like.
Oftentimes, it is desirable to test the devices on the wafer to determine which are functional and which are inoperative or partially functional. To this end, wafer testers apply power and input signals to the devices and monitor outputs during a predetermined testing routine while the devices are still on the wafer.
Because each DUT is substantially identical to the others, there can be a plurality of identical DUT probe groups. Each DUT probe group includes probes that make discrete pressure connections to separate ones of the terminals on a corresponding DUT.
These DUT probe groups can be attached to a substrate. This substrate and the probes in the DUT probe groups together form a probe head that is part of the tester system. The wafer tester typically includes multiple channels, one for each probe in the DUT probe groups on the probe head. As a result, multiple DUT probe groups simultaneously contact multiple DUTs on the wafer.
Obviously, the more DUTs that can be simultaneously tested, the faster the entire wafer can be tested. But there is a limit to the number of tester channels that can be connected to the DUT probe groups. While some testers contain many channels, e.g., 128 channels, there may be several hundred DUTs on the wafer to be tested. The testing process consequently includes bringing the DUT probe groups and terminals on a first corresponding set of DUTs into contact with one another, performing the test, lifting the probes from the DUTs, moving the probes and wafer relative to one another, bringing the probes into contact with terminals on another set of DUTs, and testing additional DUTs. This process is repeated until all the DUTs on the wafer are tested.
Efficiency is increased if a probe head having more probes in DUT probe groups than there are tester channels is used in a manner that permits rapid and effective switching of tester channels from probes in one group of DUT probe groups to probes in another DUT probe group. This can effectively reshape the number and pattern of operational DUT probe groups on the probe head.
The figures presented in conjunction with this description are views of only particular—rather than complete—portions of the devices and methods of making the devices. Together with the following description, the figures demonstrate and explain the principles of such devices and methods according to some embodiments of the invention. In the figures, the thickness of layers and regions may be exaggerated in some instances for clarity. It will also be understood that when a layer is referred to as being “on” another layer or substrate, it can be directly on the other layer or substrate, or intervening layers may also be present. The same reference numerals in different drawings represent the same element, and thus their descriptions will be omitted.